State assignment for realizing modular input-free sequential logical networks without invertors

摘要

Appearance of integrated circuits has made of great importance a problem of working out a technique of synthesis which make it possible to form the resulting logic network from identical integrated units involving a minimum number of external links. The proposed assignment made for input-free sequential logical networks has the following features.o(1)The whole sequential logical network consists of n subnetworks, exciting each of n memory elements and having identical internal structure. Besides for any two input binary sets which set i-th and j-th memory elements, respectively, such a shift on s positions exists (s≥1) where i-th input set coincides with j-th input set.(2)i-th memory element logical network (i=1,…n) is identified as two-level logic specified by the following parameters <γ1, γ2, γ3>, where γ1 is a number of gates in the first level γ2 is a number of inputs for each gate γ3 is complete number of input variables(3)The i-th logical network (i=1,…n) does not contain any invertors.