A VLSI array architecture for Hough transform
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摘要
In this article, an asynchronous array architecture for straight line Hough transform (HT) is proposed using a scaling-free modified Co-Ordinate Rotation Digital Computer (CORDIC) unit as a basic processing element (PE). It exhibits four-fold angle parallelism by dividing the Hough space into four subspaces to reduce the computation burden to 25% of the conventional requirements. A distributed accumulator arrangement scheme is adopted to ensure conflict free voting operation. The architecture is then extended to compute circular and elliptic HT given their centers and orientations. Compared to some other existing architectures, this one exhibits higher computation speed. Society. Published by
论文关键词:Hough transform,CORDIC,Low power,Image processing,Multiplierless array architecture
论文评审过程:Received 6 June 1999, Revised 1 May 2000, Accepted 1 May 2000, Available online 7 June 2001.
论文官网地址:https://doi.org/10.1016/S0031-3203(00)00080-7