Finite element analysis on distributed memory architectures

摘要

Multiprocessing is considered the only way to provide the high performance levels demanded by some present-day applications at a moderate cost. In this paper, the finite element computations are to be performed on a transputer array. the transputer is a programmable device on a single chip. In order to give a good trade-off between efficiency and memory requirements, a hybrid geometric-algorithmic parallelism is to be used. The domain of the problem is partitioned into a set of subdomains. The finite element equations are constructed in parallel then an element-by-element parallel preconditioned conjugate gradient algorithm is applied. A numerical experiment using eight transputers embedded in an IBM personal computer is presented.