Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs

作者：

Highlights：

• A dedicated co-design flow for embedded multi-core platforms has been implemented.

• The toolchain functionality is demonstrated for two different FPGA boards.

• QCIF video sequences are decoded at 45 FPS at 50 MHz.

摘要

•A dedicated co-design flow for embedded multi-core platforms has been implemented.•The toolchain functionality is demonstrated for two different FPGA boards.•QCIF video sequences are decoded at 45 FPS at 50 MHz.

论文关键词：Co-design,Reconfigurable Video Coding (RVC),Dataflow programming,Multi-Processor System-on-Chip (MPSoC),Transport-Trigger Architecture (TTA)

论文评审过程：Available online 4 September 2013.

论文官网地址：https://doi.org/10.1016/j.image.2013.08.013