An array processor approach for low bit rate video coding

摘要

In this paper a hardware for a software oriented implementation of the videophone coding algorithm with reduced resolutions according to CCITT XV/4 is described. The hardware is based on an array processor chip consisting of up to twenty active processing cells. With six of these chips, located on one board, a processing power is available that is sufficient for low bit rate video coding algorithms.Details of the array chip and the array processor board are presented. In addition a software tool is described that makes it feasible to simulate algorithms under the hardware constraints of the array processor board and to allow a direct implementation of the simulated algorithms on the array processor board, i.e. it generates the microcode and downloads the microcode into the array processor board. Results of simulations and of implementations are given.