Coding scheme and hardware structure of a high-rate digital HDTV codec with partly error-free encoding

摘要

For contributing HDTV signals inside a studio and between different studios the and cability for multiple encoding and decoding of signals without visible errors is demanded. Ideally there would be no errors at all. For that reason a rather high bit-rate of 560 Mbit/s for transmission is under discussion. To start out from an active range of 1152 lines, 1920 pels/line and a field frequency of 50 Hz, a data rate of 885 Mbit/s and a compression factor of about 1.6 is needed. The paper describes an intraframe HDTV coder which meets this condition with a simple one-dimensional DPCM and a subsequent entropy coder. Only in the cases where pure entropy coding is not sufficient, a small quantization with 6 bits for the luminance component signal and 5 or 4 bits for the chrominance component is performed. The resulting quality after coding and reconstruction is excellent for different test sequences with a signal-to-noise ratio of about 60 dB. A discussion of the hardware implementation of the proposed codec structure shows that using gate arrays makes it possible to realize nearly all of the codec components in fast CMOS technology. The critical part of the scheme, the VLC decoder, will be discussed in detail. The system frequency for coding and decoding was limited to 72 MHz.