Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models

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The design of integrated circuits (ICs) in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices on the circuits’ layout, a task that has stubbornly defied all automation attempts. In this paper, disruptive research using modern embedding techniques and a fully unsupervised attention-based encoder-decoder model is conducted to automate the placement task of analog IC layout design. The attention-based graph-to-sequence model, AGraph2Seq for short, differs from other heterogeneous graph embedding approaches by introducing structure in both the input and output data in an encoder-decoder architecture. The structure allows for a smaller and more effective placement regression model, drastically reducing the number of trainable parameters and turning the model inherently independent of the circuit topology in terms of the way devices are connected and the number of devices in a circuit, turning it easily scalable to circuits with higher complexity. Additionally, the attention mechanism makes the model’s decoder invariant to the input devices’ order. The deep model is ultimately trained in an end-to-end fashion to minimize a fully unsupervised loss function that efficiently evaluates the fulfillment of fundamental placement’s topological constraints. As a proof of concept, the final model, but also its intermediate stages, i.e., encoder-only, decoder-only, and encoder-decoder without attention, are extensively used to propose different placement solutions for several modern analog IC blocks in multiple deep nanometer technology nodes at push-button speed, including topologies not present in the training set. These present a level of generalization beyond traditional analog IC placement methodologies and most recent machine learning-based approaches and compete with or outperform highly optimized analog layouts and human-made designs.

论文关键词:Analog Integrated Circuits,Artificial Neural Networks,Automatic Layout Generation,Electronic Design Automation,Relational Graph Convolutional Networks,Node Embeddings,Physical Design,Sequence-to-sequence,Deep Learning

论文评审过程:Received 16 June 2021, Revised 9 May 2022, Accepted 21 June 2022, Available online 25 June 2022, Version of Record 29 June 2022.

论文官网地址:https://doi.org/10.1016/j.eswa.2022.117954