Two-level pipelined systolic array for multidimensional convolution

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摘要

This paper describes a systolic array for the computation of n-dimensional (nD) convolutions for any positive integer n. Systolic systems usually achieve high performance by allowing computations to be pipelined over a large array of processing elements. To achieve even higher performance, the systolic array described in this paper uses a second level of pipelining by allowing the processing elements themselves to be pipelined to an arbitrary degree.

论文关键词:signal and image processing,multidimensional convolution,systolic array,pipelined arithmetic unit,special-purpose processor,VLSI

论文评审过程:Available online 10 June 2003.

论文官网地址:https://doi.org/10.1016/0262-8856(83)90005-7