A high throughput hardware architecture for deblocking filter in HEVC

作者：

Highlights：

• Horizontal and vertical edges are filtered without the need of a transpose unit.

• Edge filter is implemented using mixed pipelining and parallel processing methods.

• Proposed DBF architecture is compatible with applications of 4 K and 8 K resolutions.

• Can achieve throughput of 322 FPS with 8 K resolution at 250 MHz operating frequency.

摘要

•Horizontal and vertical edges are filtered without the need of a transpose unit.•Edge filter is implemented using mixed pipelining and parallel processing methods.•Proposed DBF architecture is compatible with applications of 4 K and 8 K resolutions.•Can achieve throughput of 322 FPS with 8 K resolution at 250 MHz operating frequency.

论文关键词：Deblocking filter,H.265/HEVC,Pipelining,Parallel processing,Application specific integrated circuit,Field programmable gate array

论文评审过程：Received 25 May 2021, Revised 25 August 2021, Accepted 20 September 2021, Available online 4 October 2021, Version of Record 11 October 2021.

论文官网地址：https://doi.org/10.1016/j.image.2021.116517